74AHC595

The 74AHC595 is a high-speed Si-gate CMOS device. The device is an 8-bit serial-in/serial-out or parallel-out shift register with output latches.

This device features a serial input and a serial standard output for cascading. All the 8 shift register stages have the asynchronous reset function when active low. When OE is held low, the data in storage register will appear at the output. When OE is held high, all outputs except Q7S are in high-impedance state.

Both the shift register and storage register have separate clocks. The shift register clock (SHCP) is positive-edge triggered. Data is shifted on the positive-going transitions of the SHCP. The storage register clock (STCP) is also positive-edge triggered. The data in each register is transferred to the storage register on a positive-going transition of the STCP. If the SHCP and STCP are connected together, the shift register is always one clock pulse ahead of the storage register.